High-speed instruction set simulator for Movidius SHAVE core

Embedded machine vision technology provides the artificial vision intelligence to the next generation of connected devices. Movidius offfers tuned software libraries for key algorithms in deep learning, 3D depth, spatial computing and natural user interfaces. The combination of these powerful algorithms and Movidius’ ultra-low power vision processing unit (VPU) is opening up new frontiers in computer vision. However, one of the biggest hurdles to further develop vision architectures is how to efficiently support hardware and software designers with fast and accurate simulators for design space exploration and software development, especially given the rising complexity of today’s systems.

In this TTP, we are focusing on the modelling and simulation of Movidius’ vision processing unit, which is based on an very-long-instruction-word paradigm. For this we are using the GenSim/ArcSim simulation technology developed at the University of Edinburgh. Using a high-level architecture description a performance-optimised full-system simulator is generated. Industrial users can transcribe available hardware descriptions from pseudo-formal representation, e.g. often used in processor instruction set references, into a machine readable format loosely based on the popular C programming language.

Out-of-the-box we have successfully modelled Movidius’ vision processor and demonstrated a 100x performance improvement over the existing in-house simulation environment, whilst providing cycle-accurate performance estimates. Code generated by either Movidius’ compiler or assembler for the target core is supported.

Within the research projects during which GenSim/ArcSim were originally developed a stand-alone environment was created with interfaces to debuggers such as GDB. A set of APIs is supported to facilitate the integration of GenSim/ArcSim in other simulation environments. However, we did not design ArcSim/GenSim as a drop-in replacement to an existing proprietary simulation framework. System level integration will form a part of our future development in order to enable potential users to replace their existing simulators more easily with GenSim/ArcSim. As part of the TTP we developed extensions to adapt the underlying simulation engine to non-standard instruction formats and encodings used in the Movidius VPU.

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